 | Services and Modeling for Embedded Software Development |
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| Services and Modeling for Embedded Software Development |
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Application Note 13. Issue 2.1
December 2015
Copyright © 2015 Embecosm Limited
 | The document entitled "AAP: An Altruistic Processor" by of Embecosm is licensed under a Creative Commons Attribution 2.0 UK: England & Wales License. See the Legal Notice for details. |
Table of Contents
AAP is a Harvard architecture specification designed for experimenting with various features in compiler back ends. In particular it has features that are common within small deeply embedded systems, such as a dearth of registers, word address code memory and pointers that will not fit in an integer.
It is also designed to be easy to use in demonstrations and education/training. This includes hardware and simulator implementation as well as the tool chain and library implementation.
The design is based on no processor in particular, although as an open hardware design, it is inspired by the OpenRISC and RISC-V projects. There are features drawn from a wide range of processors developed over the past 30 years. Indeed the branch-and-link operation goes back even further, to the IBM 360.
| Revision History | ||
|---|---|---|
| Revision 2.1 | 10 December 2015 | |
|
The Postincrement and Predecrement store instructions defined Ra rather than Rd as the operand to which the update was applied. Postincrement, Predecement instructions now increment or decrement by the amount of the provided offset (Previously it was a fixed offset of one or two bytes for byte and word operations respectively).
| ||
| Revision 2.0 | 9 October 2015 | |
|
Issue 2.0, which covers the entire ISA. | ||
| Revision 1.9 | 8 October 2015 | |
|
Final draft before release 2.0. Adds some notation description
and a chapter for the architecture description, which
incorporates some of the old intro and the old chapter on
| ||
| Revision 1.8 | 8 October 2015 | |
|
All 32-bit instructions described. | ||
| Revision 1.7 | 8 September 2015 | |
|
First batch of 32-bit ALU instruction described. Various typos fixed. | ||
| Revision 1.6 | 8 September 2015 | |
|
All 16-bit instructions described. Encoding of
JAL corrected in the summary.
Rb used to store the PC for all
| ||
| Revision 1.5 | 8 September 2015 | |
|
16-bit ALU instruction details complete. Change opcode mnemonics for ALU instructions with constant arguments. Off-by-one encoding for immediate shift values described. | ||
| Revision 1.4 | 4 September 2015 | |
|
Structure of detailed instruction descriptions refined. Most 16-bit ALU instructions now documented. | ||
| Revision 1.3 | 4 September 2015 | |
|
All instruction formats now shown. All summaries in new format. | ||
| Revision 1.2 | 3 September 2015 | |
|
First stage of improved formatting, using LibreOffice Impress to as the basis of the instruction format diagrams for 32-bit instructions (generating SVG and PNG). Clearer summary of instructions used for 32-bit ALU instructions. | ||
| Revision 1.1 | 18 July 2015 | |
|
Start of revision process. Remove load/store double
instructions. Use second opcode field of 32-bit load/store as
extra constant field. Make all load/store offsets signed. Make
| ||
| Revision 1.0 | 14 April 2015 | |
|
Bump release number to 1.0 for issue. | ||
| Revision 0.9 | 14 April 2015 | |
|
First public release outlining the architecture. | ||
| Revision N/A | 11 April 2015 | |
|
Correct encoding of 32-bit branches (4 more bits of offset).
Correct | ||
| Revision N/A | 8 April 2015 | |
|
Full summary of all 16-bit and 32-bit instructions. | ||
| Revision N/A | 8 April 2015 | |
|
Updated preface in preparation for revised architecture. | ||
| Revision N/A | 6 April 2015 | |
|
Initial concept | ||
Figure 2.1 shows the overall structure of AAP.
These are the key features of the AAP design.
The core design sticks to the RISC principles of 3-address register-to-register operation, a small number of operations and a simple to implement data path. The fundamental data type is the 16-bit integer.
Although 32/64-bit RISC architectures typically have 16 or more general purpose registers, small deeply embedded processors often have far fewer. This represents a significant compiler implementation challenge. To allow exploration of this area, AAP can be configured with between 4 and 64 16-bit registers.
The basic architecture provides a 64k byte addressed data memory and a separate 16M word instruction memory. By requiring more than 16-bits to address the instruction memory, the compiler writer can explore the challenge of pointers which are larger than the native integer type.
Deeply embedded systems often have very small memories, particularly for data, so the size of memories can be configured.
Many architectures also provide more than two address spaces, often for special purposes. For example a small EEPROM alongside Flash memory, or the Special Purpose Register block of OpenRISC. AAP can support additional address spaces, allowing support for multiple address spaces throughout the tool chain to be explored.
AAP requires a 24-bit program counter, which is held in a 32-bit register. The top bits of the program counter then form a status register. Jump instructions ignore these top 8 bits.
At present only one status bit is defined, a carry flag to allow multiple precision arithmetic.
A frequent feature of many architectures is to provide a subset of the most commonly used parts of the Instruction Set Architecture (ISA) in a short encoding of 16-bits. Less common instructions are then encoded in 32-bits.
Optimizing to use these shorter instructions, is particularly important for compilers for embedded targets, where memory is at a premium. AAP provides such a 16-bit subset with a 32-bit encoding of the full ISA. However it follows the instruction chaining of RISC-V, so even longer instructions could be created in the future.
The fields within each 16-bit instruction are fixed. A 32-bit instruction pairs up those fields to increase the number of instructions.
AAP has stuck rigidly to the RISC principle of 3-address instructions throughout. Almost all instructions come in two variants, one where the third argument is a register, and one where the third argument is a constant.
There are no flag registers indicating the results of operations for use in conditional jumps. Instead the operation is encoded within the jump instruction itself.
There is an 8-bit status register as part of the program counter, which includes a carry flag. However this is not used for flow-of-control, but to enable multiple precision arithmetic.
The architecture is little-endian—the least significant byte of a word or double word is at the lowest address.
The behavior for instruction memory is that one word is fetched, since it may be a 16-bit instruction. If a second word is needed, then its fields are paired with the first instructions to give larger values for each field. This is done in little-endian fashion, i.e. the field from the second instruction forms the most significant bits of the combined field.
Early RISC designs introduced the concept of a delay slot after branches. This avoided pipeline delays in branch processing. Implementations can now avoid such pipeline delay, so like most modern architectures, AAP does not have delay slots.
NOP with
argument for simulator control
This idea is taken from OpenRISC. The
NOP opcode includes fields to
specify a register and a constant. These can be used in both
hardware and simulation to trigger side-effects.
Events indirect through instructions in the first 256 (0x100) words of instruction memory. In general these should be 32-bit branch instructions, which means event handlers should reside in first or last 221 words of instruction memory.
At present the following event vector locations (word addresses) are defined
0x00Power-on reset.
0x02Bus error
The event handling mechanism is still in development. In particular
no location is yet defined for the return address to be used by the
RTE instruction (see Section 3.7.1).
The NOP instruction takes an immediate argument which
can be used to trigger certain behavior in a simulator.
0 : Breakpoint
1 : Do nothing
2 : Exit with return code in Rd
3 : Write char in Rd to standard output.
4 : Write char in Rd to standard error.
All other values: do nothing, but future behavior not guaranteed.
In the instruction descriptions below, the following notation is used.
Destination register number "d" in the general registers.
First source register number "a" in the general registers.
Second source register number "b" in the general registers.
The program counter
Unsigned immediate value
Signed immediate value
Byte offset "i" in the data memory.
Word offset "i" in the code memory.
The carry flag.
The value "x" (which may be one of the above) sign extended as necessary.
Individual bits in the encodings are used as follows.
0A zero bit.
1A one bit.
Bit "n" of the destination register field.
Bit "n" of the the first source register field.
Bit "n" of the the second source register field.
Bit "n" of the the unsigned constant field.
Bit "n" of the the signed constant field.
The assembler generally follows standard GNU assembler conventions. Instructions take the following form:
[label:] opcode [arguments]
There may be up to 3 arguments, separated by commas. Registers are
indicted by R followed by a number. Constants
and constant expressions may be preceded by # for
clarity, but this is not required. C style notation to indicate the
base of constants, which defaults to decimal.
The 16-bit instruction formats are shown in Figure 3.1 and the 32-bit instruction formats in Figure 3.2.
Longer instruction formats are possible by setting the top bit of the
second word to 1. By repeating this,
instructions of arbitrary length are possible.
Table 3.1 lists all the 16-bit
ALU instructions, which have class
00;
Table 3.2 lists all the 16-bit
load/store instructions, which have class 01;
Table 3.3 lists all the 16-bit
branch/jump instructions, which have class
10; and
Table 3.4 lists all the 16-bit
miscellaneous instructions, which have class
11.
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
NOP Rd,I
| 5 |
0000000dddiiiiii
| No operation | |||||
ADD Rd,Ra,Rb
| 1 |
0000001dddaaabbb
| Unsigned add | |||||
SUB Rd,Ra,Rb
| 1 |
0000010dddaaabbb
| Unsigned subtract | |||||
AND Rd,Ra,Rb
| 1 |
0000011dddaaabbb
| Bitwise AND | |||||
OR Rd,Ra,Rb
| 1 |
0000100dddaaabbb
| Bitwise OR | |||||
XOR Rd,Ra,Rb
| 1 |
0000101dddaaabbb
| Bitwise exclusive OR | |||||
ASR Rd,Ra,Rb
| 1 |
0000110dddaaabbb
| Arithmetic shift right | |||||
LSL Rd,Ra,Rb
| 1 |
0000111dddaaabbb
| Logical shift left | |||||
LSR Rd,Ra,Rb
| 1 |
0001000dddaaabbb
| Logical shift right | |||||
MOV Rd,Ra
| 1 |
0001001dddaaa000
| Move register to register | |||||
ADDI Rd,Ra,#I
| 2 |
0001010dddaaaiii
| Unsigned add immediate | |||||
SUBI Rd,Ra,#I
| 2 |
0001011dddaaaiii
| Unsigned subtract immediate | |||||
ASRI Rd,Ra,#I
| 2 |
0001100dddaaaiii
| Arithmetic shift right immediate | |||||
LSLI Rd,Ra,#I
| 2 |
0001101dddaaaiii
| Logical shift left immediate | |||||
LSRI Rd,Ra,#I
| 2 |
0001110dddaaaiii
| Logical shift right immediate | |||||
MOVI Rd,#I
| 5 |
0001111dddiiiiii
| Move immediate to register | |||||
Table 3.1. 16-bit ALU instructions
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
LDB Rd,(Ra,S)
| 4 |
0010000dddaaasss
| Indexed load byte | |||||
LDW Rd,(Ra,S)
| 4 |
0010100dddaaasss
| Indexed load word | |||||
LDB Rd,(Ra+,S)
| 4 |
0010001dddaaasss
| Indexed load byte with postincrement | |||||
LDW Rd,(Ra+,S)
| 4 |
0010101dddaaasss
| Indexed load word with postincrement | |||||
LDB Rd,(-Ra,S)
| 4 |
0010010dddaaasss
| Indexed load byte with predecrement | |||||
LDW Rd,(-Ra,S)
| 4 |
0010110dddaaasss
| Indexed load word with predecrement | |||||
STB (Rd,S),Ra
| 4 |
0011000dddaaasss
| Indexed store byte | |||||
STW (Rd,S),Ra
| 4 |
0011100dddaaasss
| Indexed store word | |||||
STB (Rd+,S),Ra
| 4 |
0011001dddaaasss
| Indexed store byte with postincrement | |||||
STW (Rd+,S),Ra
| 4 |
0011101dddaaasss
| Indexed store word with postincrement | |||||
STB (-Rd,S),Ra
| 4 |
0011010dddaaasss
| Indexed store byte with predecrement | |||||
STW (-Rd,S),Ra
| 4 |
0011110dddaaasss
| Indexed store word with predecrement | |||||
Table 3.2. 16-bit load/store instructions
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
BRA S
| 7 |
0100000sssssssss
| Relative branch | |||||
BAL S,Rb
| 6 |
0100001ssssssbbb
| Relative branch and link | |||||
BEQ S,Ra,Rb
| 3 |
0100010sssaaabbb
| Relative branch if equal | |||||
BNE S,Ra,Rb
| 3 |
0100011sssaaabbb
| Relative branch if not equal | |||||
BLTS S,Ra,Rb
| 3 |
0100100sssaaabbb
| Relative branch if signed less than | |||||
BLES S,Ra,Rb
| 3 |
0100101sssaaabbb
| Relative branch if signed less than or equal to | |||||
BLTU S,Ra,Rb
| 3 |
0100110sssaaabbb
| Relative branch if unsigned less than | |||||
BLEU S,Ra,Rb
| 3 |
0100111sssaaabbb
| Relative branch if unsigned less than or equal to | |||||
JMP Rd
| 1 |
0101000ddd000000
| Absolute jump | |||||
JAL Rd,Rb
| 1 |
0101001ddd000bbb
| Absolute jump and link | |||||
JEQ Rd,Ra,Rb
| 1 |
0101010dddaaabbb
| Absolute jump if equal | |||||
JNE Rd,Ra,Rb
| 1 |
0101011dddaaabbb
| Absolute jump if not equal | |||||
JLTS Rd,Ra,Rb
| 1 |
0101100dddaaabbb
| Absolute jump if signed less than | |||||
JLES Rd,Ra,Rb
| 1 |
0101101dddaaabbb
| Absolute jump if signed less than or equal to | |||||
JLTU Rd,Ra,Rb
| 1 |
0101110dddaaabbb
| Absolute jump if unsigned less than | |||||
JLEU Rd,Ra,Rb
| 1 |
0101111dddaaabbb
| Absolute jump if unsigned less than or equal to | |||||
Table 3.3. 16-bit branch/jump instructions
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
RTE Rd
| 1 |
0110000ddd000000
| Return from exception | |||||
Table 3.4. Miscellaneous 16-bit instructions
In the following list, the encoding is shown with the word at the lower address first.
Table 3.5 lists all the 32-bit
ALU instructions, which have class
00xx;
Table 3.6 lists all the 32-bit
load/store instructions, which have class
01xx;
Table 3.7 lists all the 32-bit
branch/jump instructions, which have class
10xx; and
There are no 32-bit instructions in the miscellaneous class, but
if there were, they would have have class
11xx.
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
NOP Rd,I
| 14 |
1000000dddiiiiii
| No operation | |||||
0000000dddiiiiii
| ||||||||
ADD Rd,Ra,Rb
| 8 |
1000001dddaaabbb
| Unsigned add | |||||
0000000dddaaabbb
| ||||||||
SUB Rd,Ra,Rb
| 8 |
1000010dddaaabbb
| Unsigned subtract | |||||
0000000dddaaabbb
| ||||||||
AND Rd,Ra,Rb
| 8 |
1000011dddaaabbb
| Bitwise AND | |||||
0000000dddaaabbb
| ||||||||
OR Rd,Ra,Rb
| 8 |
1000100dddaaabbb
| Bitwise OR | |||||
0000000dddaaabbb
| ||||||||
XOR Rd,Ra,Rb
| 8 |
1000101dddaaabbb
| Bitwise exclusive OR | |||||
0000000dddaaabbb
| ||||||||
ASR Rd,Ra,Rb
| 8 |
1000110dddaaabbb
| Arithmetic shift right | |||||
0000000dddaaabbb
| ||||||||
LSL Rd,Ra,Rb
| 8 |
1000111dddaaabbb
| Logical shift left | |||||
0000000dddaaabbb
| ||||||||
LSR Rd,Ra,Rb
| 8 |
1001000dddaaabbb
| Logical shift right | |||||
0000000dddaaabbb
| ||||||||
MOV Rd,Ra
| 8 |
1001001dddaaa000
| Move register to register | |||||
0000000dddaaa000
| ||||||||
ADDI Rd,Ra,I
| 11 |
1001010dddaaaiii
| Unsigned add immediate | |||||
000iiiidddaaaiii
| ||||||||
SUBI Rd,Ra,I
| 11 |
1001011dddaaaiii
| Unsigned subtract immediate | |||||
000iiiidddaaaiii
| ||||||||
ASRI Rd,Ra,I
| 9 |
1001100dddaaaiii
| Arithmetic shift right immediate | |||||
0000000dddaaaiii
| ||||||||
LSLI Rd,Ra,I
| 9 |
1001101dddaaaiii
| Logical shift left immediate | |||||
0000000dddaaaiii
| ||||||||
LSRI Rd,Ra,I
| 9 |
1001110dddaaaiii
| Logical shift right immediate | |||||
0000000dddaaaiii
| ||||||||
MOVI Rd,I
| 15 |
1001111dddiiiiii
| Move immediate to register | |||||
000iiiidddiiiiii
| ||||||||
ADDC Rd,Ra,Rb
| 8 |
1000001dddaaabbb
| Add with carry | |||||
0000001dddaaabbb
| ||||||||
SUBC Rd,Ra,Rb
| 8 |
1000010dddaaabbb
| Subtract with carry | |||||
0000001dddaaabbb
| ||||||||
ANDI Rd,Ra,I
| 10 |
1000011dddaaaiii
| Bitwise AND immediate | |||||
000iii1dddaaaiii
| ||||||||
ORI Rd,Ra,I
| 10 |
1000100dddaaaiii
| Bitwise OR immediate | |||||
000iii1dddaaaiii
| ||||||||
XORI Rd,Ra,I
| 10 |
1000101dddaaaiii
| Bitwise exclusive OR immediate | |||||
000iii1dddaaaiii
| ||||||||
Table 3.5. 32-bit ALU instructions
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
LDB Rd,(Ra,S)
| 13 |
1010000dddaaasss
| Indexed load byte | |||||
000ssssdddaaasss
| ||||||||
LDW Rd,(Ra,S)
| 13 |
1010100dddaaasss
| Indexed load word | |||||
000ssssdddaaasss
| ||||||||
LDB Rd,(Ra+,S)
| 13 |
1010001dddaaasss
| Indexed load byte with postincrement | |||||
000ssssdddaaasss
| ||||||||
LDW Rd,(Ra+,S)
| 13 |
1010101dddaaasss
| Indexed load word with postincrement | |||||
000ssssdddaaasss
| ||||||||
LDB Rd,(-Ra,S)
| 13 |
1010010dddaaasss
| Indexed load byte with predecrement | |||||
000ssssdddaaasss
| ||||||||
LDW Rd,(-Ra,S)
| 13 |
1010110dddaaasss
| Indexed load word with predecrement | |||||
000ssssdddaaasss
| ||||||||
STB (Rd,S),Ra
| 13 |
1011000dddaaasss
| Indexed store byte | |||||
000ssssdddaaasss
| ||||||||
STW (Rd,S),Ra
| 13 |
1011100dddaaasss
| Indexed store word | |||||
000ssssdddaaasss
| ||||||||
STB (Rd+,S),Ra
| 13 |
1011001dddaaasss
| Indexed store byte with postincrement | |||||
000ssssdddaaasss
| ||||||||
STW (Rd+,S),Ra
| 13 |
1011101dddaaasss
| Indexed store word with postincrement | |||||
000ssssdddaaasss
| ||||||||
STB (-Rd,S),Ra
| 13 |
1011010dddaaasss
| Indexed store byte with predecrement | |||||
000ssssdddaaasss
| ||||||||
STW (-Rd,S),Ra
| 13 |
1011111dddaaasss
| Indexed store word with predecrement | |||||
000ssssdddaaasss
| ||||||||
Table 3.6. 32-bit load/store instructions
| Opcode | Format | Encoding | Description | |||||
|---|---|---|---|---|---|---|---|---|
BRA S
| 17 |
1100000sssssssss
| Relative branch | |||||
000sssssssssssss
| ||||||||
BAL S,Rb
| 16 |
1100001ssssssbbb
| Relative branch and link | |||||
000ssssssssssbbb
| ||||||||
BEQ S,Ra,Rb
| 12 |
1100010sssaaabbb
| Relative branch if equal | |||||
000sssssssaaabbb
| ||||||||
BNE S,Ra,Rb
| 12 |
1100011sssaaabbb
| Relative branch if not equal | |||||
000sssssssaaabbb
| ||||||||
BLTS S,Ra,Rb
| 12 |
1100100sssaaabbb
| Relative branch if signed less than | |||||
000sssssssaaabbb
| ||||||||
BLES S,Ra,Rb
| 12 |
1100101sssaaabbb
| Relative branch if signed less than or equal to | |||||
000sssssssaaabbb
| ||||||||
BLTU S,Ra,Rb
| 12 |
1100110sssaaabbb
| Relative branch if unsigned less than | |||||
000sssssssaaabbb
| ||||||||
BLEU S,Ra,Rb
| 12 |
1100111sssaaabbb
| Relative branch if unsigned less than or equal to | |||||
000sssssssaaabbb
| ||||||||
JMP Rd
| 8 |
1101000ddd000000
| Absolute jump | |||||
0000000ddd000000
| ||||||||
JAL Rd,Rb
| 8 |
1101001ddd000bbb
| Absolute jump and link | |||||
0000000ddd000bbb
| ||||||||
JEQ Rd,Ra,Rb
| 8 |
1101010dddaaabbb
| Absolute jump if equal | |||||
0000000dddaaabbb
| ||||||||
JNE Rd,Ra,Rb
| 8 |
1101011dddaaabbb
| Absolute jump if not equal | |||||
0000000dddaaabbb
| ||||||||
JLTS Rd,Ra,Rb
| 8 |
1101100dddaaabbb
| Absolute jump if signed less than | |||||
0000000dddaaabbb
| ||||||||
JLES Rd,Ra,Rb
| 8 |
1101101dddaaabbb
| Absolute jump if signed less than or equal to | |||||
0000000dddaaabbb
| ||||||||
JLTU Rd,Ra,Rb
| 8 |
1101110dddaaabbb
| Absolute jump if unsigned less than | |||||
0000000dddaaabbb
| ||||||||
JLEU Rd,Ra,Rb
| 8 |
1101111dddaaabbb
| Absolute jump if unsigned less than or equal to | |||||
0000000dddaaabbb
| ||||||||
JMPL Rd
| 8 |
1101000ddd000000
| Absolute jump long | |||||
0000001ddd000000
| ||||||||
JALL Rd,Rb
| 8 |
1101001ddd000bbb
| Absolute jump long and link | |||||
0000001ddd000bbb
| ||||||||
JEQL Rd,Ra,Rb
| 8 |
1101010dddaaabbb
| Absolute jump long if equal | |||||
0000001dddaaabbb
| ||||||||
JNEL Rd,Ra,Rb
| 8 |
1101011dddaaabbb
| Absolute jump long if not equal | |||||
0000001dddaaabbb
| ||||||||
JLTSL Rd,Ra,Rb
| 8 |
1101100dddaaabbb
| Absolute jump long if signed less than | |||||
0000001dddaaabbb
| ||||||||
JLESL Rd,Ra,Rb
| 8 |
1101101dddaaabbb
| Absolute jump long if signed less than or equal to | |||||
0000001dddaaabbb
| ||||||||
JLTUL Rd,Ra,Rb
| 8 |
1101110dddaaabbb
| Absolute jump long if unsigned less than | |||||
0000001dddaaabbb
| ||||||||
JLEUL Rd,Ra,Rb
| 8 |
1101111dddaaabbb
| Absolute jump long if unsigned less than or equal to | |||||
0000001dddaaabbb
| ||||||||
Table 3.7. 32-bit branch/jump instructions
Encoding (format 5):
0 | 0 | 0 | 0 | 0 | 0 | 0 | d2 | d1 | d0 | i5 | i4 | i3 | i2 | i1 | i0 |
Syntax:
NOP Rd,I
Constraints:
Outcome:
Notes:
This opcode may trigger side-effects in implementations, depending on the value of I, particularly when simulating (see Section 2.3).
All implementations should use d = 0, I = 0 as the break instruction for debugging, which should halt the processor.
All implementations should use d = 0, I = 1 as a true no-operation instruction.
The rationale behind this decision is that in an erroneous program, the most likely value to be encountered as a random instruction is zero, which will stop the processor.
Encoding (format 1):
0 | 0 | 0 | 0 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
ADD Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 1):
0 | 0 | 0 | 0 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
SUB Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 1):
0 | 0 | 0 | 0 | 0 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
AND Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 1):
0 | 0 | 0 | 0 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
OR Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 1):
0 | 0 | 0 | 0 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
XOR Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 1):
0 | 0 | 0 | 0 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
ASR Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 17 the result in Rd will be zero.
The carry flag is always cleared, even if a shift of zero is specified.
Encoding (format 1):
0 | 0 | 0 | 0 | 1 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
LSL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 16 the result in Rd will be zero.
Encoding (format 1):
0 | 0 | 0 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
LSR Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 16 the result in Rd will be zero.
Encoding (format 1):
0 | 0 | 0 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | 0 | 0 | 0 |
Syntax:
MOV Rd,Ra
Constraints:
Outcome:
Encoding (format 2):
0 | 0 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
Syntax:
ADDI Rd,Ra,I
Constraints:
Outcome:
Notes:
Adding constant zero can be used to clear the carry flag.
Encoding (format 2):
0 | 0 | 0 | 1 | 0 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
Syntax:
SUBI Rd,Ra,I
Constraints:
Outcome:
Encoding (format 2):
0 | 0 | 0 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
Syntax:
ASRI Rd,Ra,I
Constraints:
Outcome:
Notes:
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 2):
0 | 0 | 0 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
Syntax:
LSLI Rd,Ra,I
Constraints:
Outcome:
Notes:
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 2):
0 | 0 | 0 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
Syntax:
LSRI Rd,Ra,I
Constraints:
Outcome:
Notes:
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 4):
0 | 0 | 1 | 0 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDB Rd,(Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 0 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDW Rd,(Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 0 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDB Rd,(Ra+,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 0 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDW Rd,(Ra+,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 0 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDB Rd,(-Ra,S)
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 0 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
LDW Rd,(-Ra,S)
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STB (Rd,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STW (Rd,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STB (Rd+,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STW (Rd+,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STB (-Rd,S),Ra
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 4):
0 | 0 | 1 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
Syntax:
STW (-Rd,S),Ra
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
![[Note]](./images/note.png) | Note |
|---|---|
|
The only branch/jump comparisons provided are for "equal", "not equal", "less than" and "greater than". Branch/jump comparisons for "less than or equal" and "greater than or equal" can be provided by using "greater than" and "less than" respectively in the opposite direction." Purists will point out that this reduces the opportunity for branch prediction and pipeline preservation. However the limited instruction space means not all opcodes can be provided. |
Encoding (format 7):
0 | 1 | 0 | 0 | 0 | 0 | 0 | s8 | s7 | s6 | s5 | s4 | s3 | s2 | s1 | s0 |
Syntax:
BRA S
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 6):
0 | 1 | 0 | 0 | 0 | 0 | 1 | s5 | s4 | s3 | s2 | s1 | s0 | b2 | b1 | b0 |
Syntax:
BAL S,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 0 | 1 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BEQ S,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 0 | 1 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BNE S,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 1 | 0 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BLTS S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 1 | 0 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BLES S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 1 | 1 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BLTU S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 3):
0 | 1 | 0 | 0 | 1 | 1 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
BLEU S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | 0 | 0 | 0 | 0 | 0 | 0 |
Syntax:
JMP Rd
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | 0 | 0 | 0 | b2 | b1 | b0 |
Syntax:
JAL Rd,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JEQ Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JNE Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JLTS Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JLES Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JLTU Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 1):
0 | 1 | 0 | 1 | 1 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
Syntax:
JLEU Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
At this time, this section is incomplete.
Encoding (format 14, first word at lower address):
1 | 0 | 0 | 0 | 0 | 0 | 0 | d2 | d1 | d0 | i5 | i4 | i3 | i2 | i1 | i0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | i11 | i10 | i9 | i8 | i7 | i6 |
Syntax:
NOP Rd,I
Constraints:
Outcome:
Notes:
This opcode may trigger side-effects in implementations, depending on the value of I, particularly when simulating (see Section 2.3).
There are no conventions for any values of d or I for the 32-bit version of NOP.
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
ADD Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
SUB Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 0 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
AND Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
OR Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
XOR Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
ASR Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 17 the result in Rd will be zero.
The carry flag is always cleared, even if a shift of zero is specified.
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 1 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
LSL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 16 the result in Rd will be zero.
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
LSR Rd,Ra,Rb
Constraints:
Outcome:
Notes:
If Rb ≥ 16 the result in Rd will be zero.
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | 0 | 0 | 0 |
Syntax:
MOV Rd,Ra
Constraints:
Outcome:
Encoding (format 11, first word at lower address):
1 | 0 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | i9 | i8 | i7 | i6 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
ADDI Rd,Ra,I
Constraints:
Outcome:
Notes:
Adding constant zero can be used to clear the carry flag.
Encoding (format 11, first word at lower address):
1 | 0 | 0 | 1 | 0 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | i9 | i8 | i7 | i6 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
SUBI Rd,Ra,I
Constraints:
Outcome:
Encoding (format 9, first word at lower address):
1 | 0 | 0 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
ASRI Rd,Ra,I
Constraints:
Outcome:
Notes:
If I ≥ 17 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 9, first word at lower address):
1 | 0 | 0 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
LSLI Rd,Ra,I
Constraints:
Outcome:
Notes:
If I ≥ 16 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 9, first word at lower address):
1 | 0 | 0 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
LSRI Rd,Ra,I
Constraints:
Outcome:
Notes:
If I ≥ 16 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag, since there are other ways of clearing the it (for example adding constant zero).
Encoding (format 15, first word at lower address):
1 | 0 | 0 | 1 | 1 | 1 | 1 | d2 | d1 | d0 | i5 | i4 | i3 | i2 | i1 | i0 |
0 | 0 | 0 | i15 | i14 | i13 | i12 | d5 | d4 | d3 | i11 | i10 | i9 | i8 | i7 | i6 |
Syntax:
MOVI Rd,I
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
ADDC Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 8, first word at lower address):
1 | 0 | 0 | 0 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
SUBC Rd,Ra,Rb
Constraints:
Outcome:
Encoding (format 10, first word at lower address):
1 | 0 | 0 | 0 | 0 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | i8 | i7 | i6 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
ANDI Rd,Ra,I
Constraints:
Outcome:
Encoding (format 10, first word at lower address):
1 | 0 | 0 | 0 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | i2 | i1 | i0 |
0 | 0 | 0 | i8 | i7 | i6 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | i5 | i4 | i3 |
Syntax:
ORI Rd,Ra,I
Constraints:
Outcome:
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDB Rd,(Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDW Rd,(Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDB Rd,(Ra+,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDW Rd,(Ra+,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDB Rd,(-Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 0 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
LDW Rd,(-Ra,S)
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STB (Rd,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
0 | 0 | 1 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STW (Rd,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STB (Rd+,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STW (Rd+,S),Ra
Constraints:
Outcome:
Notes:
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STB (-Rd,S),Ra
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
Encoding (format 13, first word at lower address):
1 | 0 | 1 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | s2 | s1 | s0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | d5 | d4 | d3 | a5 | a4 | a3 | s5 | s4 | s3 |
Syntax:
STW (-Rd,S),Ra
Constraints:
Outcome:
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte address. Accessing a non-existent memory location will trigger a bus error exception.
| Note |
|---|---|
|
As with the 16-bit instructions, only a limited range of comparisons is provided. See Section 3.6 for an explanation. |
Encoding (format 17, first word at lower address):
1 | 1 | 0 | 0 | 0 | 0 | 0 | s8 | s7 | s6 | s5 | s4 | s3 | s2 | s1 | s0 |
0 | 0 | 0 | s21 | s20 | s19 | s18 | s17 | s16 | s15 | s14 | s13 | s12 | s11 | s10 | s9 |
Syntax:
BRA S
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 16, first word at lower address):
1 | 1 | 0 | 0 | 0 | 0 | 1 | s5 | s4 | s3 | s2 | s1 | s0 | b2 | b1 | b0 |
0 | 0 | 0 | s18 | s17 | s16 | s15 | s14 | s13 | s12 | s11 | s10 | s9 | b5 | b4 | b3 |
Syntax:
BAL S,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 0 | 1 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BEQ S,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 0 | 1 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BNE S,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 1 | 0 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BLTS S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 1 | 0 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BLES S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 1 | 1 | 0 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BLTU S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 12, first word at lower address):
1 | 1 | 0 | 0 | 1 | 1 | 1 | s2 | s1 | s0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | s9 | s8 | s7 | s6 | s5 | s4 | s3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
BLEU S,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | d5 | d4 | d3 | 0 | 0 | 0 | 0 | 0 | 0 |
Syntax:
JMP Rd
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | 0 | 0 | 0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | 0 | 0 | 0 | b5 | b4 | b3 |
Syntax:
JAL Rd,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JEQ Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JNE Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLTS Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLES Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLTU Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLEU Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 0 | 0 | d2 | d1 | d0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | 0 | 0 | 0 | 0 | 0 | 0 |
Syntax:
JMPL Rd
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 0 | 1 | d2 | d1 | d0 | 0 | 0 | 0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | 0 | 0 | 0 | b5 | b4 | b3 |
Syntax:
JALL Rd,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jumping to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JEQL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 0 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JNEL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 0 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLTSL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 0 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLESL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 1 | 0 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLTUL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Encoding (format 8, first word at lower address):
1 | 1 | 0 | 1 | 1 | 1 | 1 | d2 | d1 | d0 | a2 | a1 | a0 | b2 | b1 | b0 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | d5 | d4 | d3 | a5 | a4 | a3 | b5 | b4 | b3 |
Syntax:
JLEUL Rd,Ra,Rb
Constraints:
Outcome:
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be a word address.
Jump to a non-existent location will trigger a bus error exception.
Because of the variability in the architecture it is difficult to be
too rigid on the ABI. In any case part of the
purpose of this architecture to allow exploration of different
ABI's. Within this section, the identifier
Rmax is used to indicate the
highest numbered register in the architecture.
The meanings of the following registers are defined.
R0: Link Register
R1: Stack Pointer
Note in particular no frame pointer is defined. It is up to the implementer to decide policy with regard to use of a frame pointer.
Again this is flexible, particularly where there can be very few registers. These are the general guidelines.
All byte arguments are promoted to 16-bits.
Arguments are passed in
R2–R7 (or
R2–Rmax
if there are fewer than 8 registers).
Results are returned on the same registers used to pass arguments.
Varargs are always passed on the stack.
A good guideline is that approximately one third of unallocated
registers should be caller saved, although that can increase to
one half where there are plenty of registers. The following
registers (if present) are caller saved: R10,
R13, R16,
R19, R22,
R25, R28,
R31, R33,
R35, R37,
R39, R41,
R43, R45,
R47, R49,
R51, R53,
R55, R57,
R59, R61 and
R63.
