I have been accepted to give one of the Main Track talks at FOSDEM 2018 on EDSAC and Chip Hack 2017! Hooray!
FOSDEM is the Free and Open Source Developers European Meeting. It is a free-to-attend annual event at ULB Solbosch Campus, Brussels, Belgium and is the largest open source conference in Europe. There are Developer Rooms devoted to a single subject such as LLVM, Lightning Talks which are 15 minutes long, and Main Track talks. The Main Track talks are 50 minutes in duration and can cover any topic for an audience with varied technical knowledge.
For mine, I will be telling the story of Chip Hack 2017 (for a wrap-up see my 18th September blog post). I shall talk about putting the EDSAC peripherals together in a way that was cheap and easy, while keeping to the original designs as closely as possible. For example, the original plan for the initial orders front panel was to use a toggle switch per instruction, but this would have become too costly.
The history of EDSAC will also be discussed, with some practical demonstrations of the peripherals made to interface with the Verilog EDSAC. I will try to show off the annoyingly noisy delay line prototype as well, to help further the understanding of the audience.
To finish off the story, I will end with looking at the current reconstruction of EDSAC by the BCS.
If you are interested in going to my talk, FOSDEM is the 3rd and 4th of February. I have yet to be given the timing for this, but I shall update you all when I know. If you have any questions or suggestions for my talk, please feel free to contact me.