Note
	These tests are not needed to fully test the integrated assembly implementation and will be superseded by future tests, but are explained here for testing the assembly parser if implemented separately from the other components.

Tests for assembly parsing should consist of an instance of each instruction in the target's instruction set, along with the expected output from llvm-mc -show-inst. An example is shown and explained below.

# RUN: llvm-mc -arch=or1k -show-inst %s | FileCheck %s

    l.add r1, r2, r3
# CHECK: <MCInst #{{[0-9]+}} ADD
# CHECK-NEXT: <MCOperand Reg:2>
# CHECK-NEXT: <MCOperand Reg:3>
# CHECK-NEXT: <MCOperand Reg:4>>
        

Each test consists of the instruction, which in this case is an add, followed by a CHECK line for the mnemonic and for each operand. The first CHECK line searches for the mnemonic, whose name was set in the TableGen declaration, in this case ADD. It does not matter about the internal value of this operand, so a search for {{[0-9]+}} matches any value as valid.

Next each operand is tested; CHECK-NEXT ensures that a test only passes if the line immediately follows the previous check line, i.e. that the operands specified belong with the instruction mnemonic specified in the previous line. In this case, registers 1, 2 and 3 were specified in the instruction then tests for register number 2, 3 and 4 are carried out, which are the internal representation of these registers.

The same is applied for immediate operands, except that the MCOperand type is Imm and it is expected that the immediate is the same as that in the instruction, not increased by one.

For OpenRISC 1000 , tests for memory operands are carried out by checking for the register operand first and then the immediate on the line that follows (i.e. the same order that they were pushed to the operands when defining ParseInstruction).

Tests can be called in the usual way and should all pass if instructions are well defined in TableGen.