Chapter 1. Introduction

This document describes a cycle accurate SystemC interface for JTAG (IEEE 1149.1).

This interface simplifies a number of common practical problems:

Interfacing to cycle accurate SystemC models created from RTL using tools such as Verilator, ARC VTOC or Carbon Design Systems SpeedCompiler.
Interfacing to traditional event driven simulators, such as Cadence NC, Synopsys VCS and Mentor Graphics ModelSim using SystemC co-simulation.
Implementing SystemC test benches which drive physical hardware via JTAG
Interfacing to external tools such as debuggers. For example to develop versions of GDB which can work through JTAG ports.

Using JTAG with SystemC

1.1. Rationale