Chapter 6. Summary

This application note has shown how to build and optimize a GDB RSP interface to a cycle accurate model of a complete SoC in SystemC. The steps can be summarized as:

Implement an interface which can read and write RSP packets from and to TCP/IP
Implement a model for the target's debug interface, which generates JTAG register actions.
Implement the main GDB server class, which maps actions requested in RSP packets to the functionality of the debug interface.
Use caching to minimize the number of JTAG register actions
Use C++ compiler options to maximize the performance of the GDB server.

The result is a GDB interface to a cycle accurate SystemC model of a complete SoC, with a performance which makes low-level firmware development a quite feasible activity.

Suggestions for corrections or improvements are welcomed. Please contact the author at jeremy.bennett@embecosm.com.