The overall structure of the system is shown in Figure 4.1.
The top level SystemC module is the GDB Server. This relies on the RSP packet interface to communicate over TCP/IP with the GDB client. It uses a model of the OpenRISC 1000 Debug Unit to talk to the cycle accurate model of ORPSoC. The Debug Unit in turn uses the Embecosm JTAG interface, allowing it to keep its JTAG interactions at a high level.
The model side is implemented in SystemC, the RSP interface in plain C++.
This structure is reflected in the top level class diagram, shown in
Figure 4.2. The SystemC classes are C++
classes which have sc_module
as a base
class. By convention SystemC classes have the suffix
SC
and Verilator generated model classes have the
prefix V
followed by the name of the top level
Verilog module.