3.8.1. Command Files

The Verilog source files and header directories to be used when modeling are specified in command files in the sim and verilator-model directories for event driven simulation and cycle accurate SystemC modeling respectively. The default is cf-baseline.scr, but an alternative may be specified through the COMMAND_FILE macro. For example.

make simulate COMMAND_FILE=cf-baseline-5.scr

When writing command files, a number of macros may be used for clarity.

$BENCH_DIR: Replaced by the location of the original ORPSoC test bench Verilog directory. This depends on where the code has been unpacked. For example if it is in ~/orp_soc, then this macro will be replaced by ~/orp_soc/bench/verilog.
$RTL_DIR: Replaced by the location of the original ORPSoC device Verilog directory. This depends on where the code has been unpacked. For example if it is in ~/orp_soc, then this macro will be replaced by ~/orp_soc/rtl/verilog.
$BENCH_LOCAL: Replaced by the location of the directory containing custom test bench Verilog. This is always in a fixed place in the hierarchy and the macro will be replaced by a reference to bench/verilog.
$RTL_LOCAL: Replaced by the location of the directory containing custom device Verilog. This is always in a fixed place in the hierarchy and the macro will be replaced by a reference to rtl/verilog.