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High Performance SoC Modeling with Verilator

A Tutorial for Cycle Accurate SystemC Model Creation and Optimization

Jeremy Bennett

Embecosm

Application Note 6. Issue 1

February 2009

Copyright © 2009 Embecosm Limited

Creative Commons License

The document entitled " High Performance SoC Modeling with Verilator " by Jeremy Bennett of Embecosm is licensed under a Creative Commons Attribution 2.0 UK: England & Wales License. See the Legal Notice for details.

Table of Contents

1. Introduction

1.1. Target Audience

1.2. Open Source

1.3. Further Sources of Information

1.3.1. Written Documentation
1.3.2. Other Information Channels

1.4. About Embecosm

2. Overview of Technologies and Tools

2.1. Cycle Accurate Modeling

2.1.1. Level of Modeling Detail
2.1.2. Tool Support
2.1.3. Modeling Language

2.2. OSCI SystemC IEEE 1666

2.3. OpenCores and the OpenRISC Project

2.3.1. The OpenRISC Reference Platform System-on-Chip (ORPSoC)

2.4. Icarus Verilog

2.5. Verilator

3. The Example Design

3.1. Memory Map

3.2. Interrupt Assignment

3.3. Test Bench Modeling of Peripherals

3.4. Test Software Application

3.5. Use of the OpenRISC 1000 l.nop Instruction

3.6. Module Hierarchy and File Organization

3.6.1. Distribution Code Organization

3.7. Modifications to the ORPSoC Code

3.8. Building the Example

3.8.1. Command Files
3.8.2. Additional Flags

4. Building the Baseline Simulation

4.1. The Command File
4.2. Running the Baseline Simulation
4.3. Baseline Simulation Performance

5. The SystemC Test Bench

5.1. The SystemC Modules of the Test Bench

5.1.1. Vorpsoc_fpga_top
5.1.2. Or1200MonitorSC
5.1.3. ResetSC
5.1.4. TraceSC and OrpsocAccess

5.2. Putting the System Together

5.2.1. sc_main

6. Building the Initial Verilator Model

6.1. Fixing the Initial Errors

6.2. Accessing Signals in Verilator Models

6.2.1. Module Hierarchy When Accessing Signals
6.2.2. Direct Access to Verilator Model Signals
6.2.3. Access to Verilator Model Signals via Tasks and Functions
6.2.4. Good Coding Practice when Accessing Verilator Signals

6.3. VCD Tracing

6.3.1. Constructor for the VCD Trace Module
6.3.2. Destructor for the VCD Trace Module
6.3.3. The trace method, driveTrace

6.4. Building the Complete Model

6.5. Baseline Verilator Performance

6.5.1. Comparison with Event Driven Simulation

7. Optimizing the Verilator Model

7.1. A Note on Statistics

7.2. Verilator Warnings

7.2.1. The CASEX Warning
7.2.2. The VARHIDDEN Warning
7.2.3. The IMPLICIT Warning
7.2.4. The WIDTH Warning
7.2.5. The CASEINCOMPLETE Warning
7.2.6. The COMBDLY Warning
7.2.7. The UNOPTFLAT Warning
7.2.8. Fixing Language Conflicts
7.2.9. Summary of Performance Gains from Verilator Warnings

7.3. C++ Compiler Optimizations

7.3.1. Use of OPT_FAST, OPT_SLOW and OPT
7.3.2. Choice of optimization level
7.3.3. Compiler Profiling

7.4. Profiling the Completed Model

7.5. Summary of Performance Gains Through Optimization

Next

Chapter 1. Introduction

Copyright © 2009 Embecosm Limited