To facilitate building the models, a Makefile
is
provided in the top level directory. Three targets are
provided.
make simulate will run an event driven
simulation using Icarus Verilog (in the sim
sub-directory).
make verilate will build and then run a SystemC cycle accurate model using Verilator
make clean will clean out all generated files.
For the simulate target, the time used by the iverilog compilation and the vvp execution are recorded (with time -p).
For the verilate target, the time used to create the Verilated model and the execution time of the complete SystemC model are recorded (also with time -p).