Verilator is a synthesis technology, so will reject any non-synthesizable constructs. This can be a particular problem with third party models of memories.

Verilator by default handles Verilog 1995, 2001, 2005 and SystemVerilog. The last can be a particular nuisance, since SystemVerilog contains a number of new keywords, which can break older Verilog code (for example do is now a keyword, but has commonly been used as the name for the data out port of a memory).

Verilator has a very strict linting system, which flags issues which can affect model performance.