6.5.1. Comparison with Event Driven Simulation

These figures cannot be compared immediately against the results for Icarus Verilog in Section 4.3. The Verilator results were obtained after several RTL code modifications. So a re-run of Icarus Verilog is needed with the same file list used with Verilator (but with the Verilog test bench files added back).

make simulate COMMAND_FILE=cf-baseline-5.scr NUM_RUNS=1000

Total processor time for elaboration was 1.77 s and for simulation was 793.33 s, corresponding to a simulation performance of 1.49 kHz.

The data for the three runs (baseline Icarus Verilog, baseline Verilator, revised Icarus Verilog) are shown in Table 6.1.

Run Description	Build Time	Run Time	Performance
Baseline Icarus Verilog	1.78 s	796.84 s	1.48 kHz
Baseline Verilator	13.94 s	27.67 s	42.66 kHz
Revised Icarus Verilog	1.77 s	793.33 s	1.49 kHz

Table 6.1. Comparison of model performance with Icarus Verilog and Verilator.

Even on gross performance, Verilator is much faster than Icarus Verilog. This is expected, since Verilator is only 2-state and gives no modeling inside clock cycles.

Icarus Verilog shows no significant performance gain from the changes made to get the design through Verilator. This is perhaps surprising, given this involved substituting simpler models for flash and SRAM.

On the critical measure of model performance, Verilator (in this example) is nearly 30 times faster than event driven simulation with Icarus Verilog.