The final fix is to remove the constructs which conflict with SystemVerilog. This gives greatest flexibility in future development. These are errors, so will stop the compilation at the first error. The model build is run without restricting the language:

make verilate COMMAND_FILE=cf-optimized-7.scr
	

The first error is in eth_wishbone-3.v:

%Error: ../local/rtl/verilog/ethernet/eth_wishbone-3.v:579: syntax error, unexpe
cted do, expecting IDENTIFIER
%Error: Cannot continue
%Error: Command Failed /home/jeremy/tools/verilator/verilator-3.700/verilator_bi
n -Mdir . -sc -f v-processed.scr
	

This is the commonest trap set by SystemVerilog's new keywords. do is often used in designs to designate the data output. The problem is fixed by simple substitution.

In this case the problem is the instantiation of eth_spram_256x32.v in eth_wishbone-3.v, which uses do for its data output port. The solution is to replace do with data_o. For consistency, di is changed to data_i at the same time.

This is the only such conflict in the ORPSoC source. A performance run with the update command file (cf-optimized-8.scr) yields no significant change in performance at 47.5 kHz excluding Verilator model build time.