Table 7.1 shows the performance gains which can be achieved by fixing the various Verilator warnings and language inconsistencies.
Run Description |
Build Time |
Run Time |
Performance |
---|---|---|---|
Baseline |
13.94 s |
27.67 s |
42.66 kHz |
|
13.91 s |
27.59 s |
42.76 kHz |
|
13.91 s |
27.66 s |
42.66 kHz |
|
13.89 s |
27.77 s |
42.50 kHz |
|
13.92 s |
27.41 s |
43.04 kHz |
|
13.93 s |
27.24 s |
43.31 kHz |
|
13.92 s |
27.32 s |
43.20 kHz |
|
13.95 s |
25.07 s |
47.06 kHz |
SystemVerilog compliant |
13.91 s |
24.85 s |
47.49 kHz |
Table 7.1. Comparison of model performance when fixing Verilator warnings.
The table confirms that the majority of warnings do not greatly
affect performance. They are primarily about writing good quality
RTL. However fixing UNOPTFLAT
gave a significant
performance improvement.