4.3.3. SprCache class

4.3.3. `SprCache` class

The OpenRISC 1000 provides for up to 2¹⁶ Special Purpose Registers (SPRs). These are frequently accessed to implement debugging commands, yet do not change when the CPU is stalled (but see the issue concerning the Next Program counter in Section 4.6.1).

In practice only a few SPRs are used repeatedly. It makes sense to cache the SPRs in a simple closed hash table. SprCache represents the cache as three private C++ arrays. The Boolean array sprIsvalid indicates whether than entry is valid, the sprKeyNum array holds the SPR value for which this entry is valid and sprValue holds the corresponding cached value. Clearing the cache is a matter of setting all entries in sprIsValid to false using memset.

A key feature is that the Next Program Counter (NPC) must always be cached (see Section 4.6.1). The cache will reject attempts to write once it is 70% full (so caching remains efficient). However a flag may be used to force caching beyond this point. This is safe, because it is only ever used for one register, the NPC

The use of SprCache within the Debug Unit is discussed in the chapter on optimization (Section 5.2).

The public interface to SprCache is as follows:

SprCache. Constructor. Allocates the arrays and calls clear to reset the cache.
~SprCache. Destructor. Deletes the arrays.
clear. Clears the cache by using memset to set all entries in sprIsValid to false.
write. Writes a value for a SPR into the cache. Will do nothing if the cache is 70% full, unless a flag parameter is set to force caching (used for NPC).
read. Returns true if a SPR is in the cache. The cached value is returned by reference through the second argument.