The global hardware and software community is developing a huge range of RISC-V based solutions. As part of its commitment to that community, Embecosm is making freely available pre-built up-to-date GCC tool chains. This will ensure that software is built with the latest RISC-V compiler features and optimizations.
Read moreIntroduction I have been exploring the capabilities of the Google Coral development board and working towards a functional face recognition implementation on the embedded device. In a previous blogpost, I discussed an overall view of how the problem might be approached. In this blog post, I dive into more detail on the very first part […]
Read moreOur very own Mary Bennett was last night announced as one of the winners of the TechWorks UKESF Scholar of the Year award. Mary is a software tool chain engineer at Embecosm, a masters student at the University of Surrey and the Champion of Academia and Training for the RISC-V Foundation. CGEN Simulator Mary has […]
Read moreIntroduction One of the currently proposed draft ISA extensions for RISC-V is the Bit Manipulation Instructions extension (from henceonwards referred to as the “Bitmanip” or “BMI” extension.) It proposes to provide fast and direct instructions for commonly-used bitwise operations, often found in cryptographic, logarithmic, bit-counting, and logical operations. The GCC toolchain work has been developed […]
Read moreIntroduction The RISC-V Instruction Set Manual describes the current status of the RISC-V ISA and its extensions. Among these there’s a mention of the ‘B’ extension that is meant to host specific instructions for bit manipulation operations. A well known proposal for such extension comes from Claire Wolf and can be found here. We implemented an […]
Read moreIntroduction In this blog post we give an introduction to the topic of facial recognition and describe our approach to the problem introduced in the previous blog post. When deciding to implement facial recognition, FaceNet was the first thing that came to mind. FaceNet is a face recognition pipeline that learns mapping from faces to […]
Read moreWhat is RI5CY? RI5CY is a 4-stage in-order pipelined RISC-V core written in SystemVerilog. It has become very popular for many applications, including being adopted as the first Core-V core in the OpenHW Group family, as well as being proposed as the reference for EmBench, a benchmark for embedded processors initiated by David Patterson and […]
Read moreIntroduction My name is Pietra Ferreira Tadeu Madio and I’m an AI Research Engineer working at Embecosm. During the summer I was able to start working full-time on my own AI-driven project. Artificial intelligence is typically associated with high power computing and big data, but there is an increasing need for development of AI systems […]
Read moreProject requirements When I arrived at Embecosm, on the first day of my work experience, I was offered a real-world project at a local church, which is being used as a nursery for toddlers. There had been noise complaints surrounding the nursery from the nearby residents. I was given the task of finding a way […]
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