Blog

22 September 2026

Howto: Bringing up IREE on a Bare Metal Microcontroller (Full Series)

A common perception is that all AI needs a great deal of compute power. Yet many AI inference models run successfully on the very smallest of processors.

Since September 2026, we have been publishing a series of posts, showing how the IREE MLIR tool flow can be used to bring up AI models on small bare metal microcontrollers. This post conveniently brings together all those posts.

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20 October 2026

Howto: Bringing up IREE on a Bare Metal Microcontroller (Part 3)

IREE compiles a model once on your workstation and runs it on bare metal with a small C runtime. In Part 3 we follow a matrix multiplication from MLIR down to RISC-V, run it on one core of a four-core CV32E40Pv2 cluster, and measure what it costs against the same calculation written by hand in C.

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7 October 2026

Howto: Bringing up IREE on a Bare Metal Microcontroller (Part 2)

In Part 2 we build a cycle-accurate Verilator model of a four-core CV32E40Pv2 cluster, run our first programs on it, and measure what memory costs: twenty cycles for a core to reach off-core memory, and when it pays to copy data into the fast local scratchpad first.

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29 September 2026

Adding CORE-V SIMD Code Generation to GCC

This summer I have been working on adding auto-vectorization for CORE-V’s SIMD (Single Instruction, Multiple Data) extension in GCC. CORE-V SIMD was developed by the PULP project at ETH Zürich and the University of Bologna. It is similar to, but predates, the proposed RISC-V P extension. The work here is based on the OpenHW Foundation’s […]

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Block diagram of the emmtrix processor cluster. A barrier peripheral sits above four CPU cores, each labelled cv32E40Pv2, each paired with its own 256 KiB scratchpad SRAM and DMA engine. All four cores connect through an instruction arbiter and a data arbiter (both round robin) down to a single 64 MiB main memory block with two independent ports.
22 September 2026

Howto: Bringing up IREE on a Bare Metal Microcontroller (Part 1)

IREE compiles a machine learning model into native code for your target, instead of interpreting it through a fixed library of kernels. In Part 1 we explain why that suits a small bare metal microcontroller, compare it with ExecuTorch, and introduce the four-core CV32E40Pv2 cluster this series runs on.

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14 September 2026

Howto: ExecuTorch AI Inference on Bare Metal MPUs

There is a common misconception that modern AI needs a large data center and lots of GPUs to run. However there are a great many very useful AI models which can run inference on much smaller devices.

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28 May 2026

IREE and ExecuTorch on Bare Metal Microcontrollers

Over past months I have posted a great deal about our work bringing up the ExecuTorch AI framework on bare metal microcontrollers. Much of this work has been done in collaboration with our colleagues at Mosaic SoC. This is true Edge AI, where we run real world AI models on hardware that is small enough […]

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2 March 2026

Running AI models on a microcontroller

A few of weeks ago, I was at FOSDEM and then the AI Plumbers conference in Brussels with my colleagues Pietra Ferreira, Shane Slattery and William Jones. While many of the talks focused on LLMs, the Embecosm team attracted a great deal of interest for our work bringing up PyTorch/ExecuTorch on a bare metal microcontroller. […]

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20 May 2025

Comparing RISC-V compilers

In my last post I looked at how the tools we use in open source development can be used to assess the health of our communities. Recently I used those same techniques as part of a poster I presented at the RISC-V European Summit comparing GCC and LLVM for RISC-V. I focused particularly on RISC-V […]

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