The ORPSoC JTAG interface uses a 4-bit instruction register with a number of custom instructions. One such instruction CHAIN is used to select the custom CHAIN register. This instruction has the binary value 0011.

The code to write the CHAIN instruction into the instruction register is:

sc_core::sc_event *actionDone = new sc_core::sc_event();
TapActionIRScan   *iRScan;

iRScan = new TapActionIRScan (actionDone, CHAIN_SELECT_IR, JTAG_IR_LEN);
tapActionQueue->write (iRScan);
wait (*actionDone);

delete iRScan;
      

The action is created as a new instance of TapActionIRScan, passing in a SystemC event for signaling completion, with the value of the instruction (CHAIN_SELECT_IR, binary 0011) and the instruction register length (JTAG_IR_LEN, 4 in the case of ORPSoC).

	Note
	In this case the SystemC event, actionDone is not deleted. It will be reused for the following data register write action (see Section 4.3).

The results are again traced in a VCD and shown in Figure 4.3.

Figure 4.3.  VCD trace of a JTAG instruction register write request

The instruction register write action commences at 1.6μs. A sequence of 0-1-1-0-0 on TMS takes the state machine from its starting point of Test-Logic-Reset through Run-Test/Idle, Select-DR-Scan, Select-IR-Scan and Capture-IR to Shift-IR.

At this point a sequence of four TMS=0, starting at 2.0μs allow the bits of the instruction register to be shifted in from TDI. The sequence 1-1-0-0 can be seen on jtag_tdi. Since the bits are shifted in least-significant bit first, this represents the binary number 0011, the CHAIN instruction.

A sequence of 1-1 on TMS moves the state machine through Exit1-IR to Update-IR at which point completion is signaled (2.5μs).