The ORPSoC JTAG CHAIN instruction selects the debug unit's 12-bit CHAIN register as the data register to be written.

The code to write the data into the CHAIN data register is:

uint64_t  dReg = 0x4;
dReg |= crc8 (chain, 4) << 4;

dRScan = new TapActionDRScan (actionDone, dReg, 12);
tapActionQueue->write (dRScan);
wait (*actionDone);

delete dRScan;
delete actionDone;
      

The 12-bit data is built up in dReg from a value (bits 0-3) and a CRC (bits 4-11). The action is created as a new instance of TapActionDRScan, passing in a SystemC event for signaling completion (reusing the signal from the instruction register write earlier), with the data value and the data register length. In this example the 12-bit value is 0000_1110_0100.

The results are again traced in a VCD and shown in Figure 4.4.

Figure 4.4.  VCD trace of a "small" JTAG data register write request

The data register write action commences at 2.6μs. The TAP state machine is currently at Update-IR from the previous write of an instruction register. A TMS sequence of 1-0-0 takes the state through Select-DR-Scan and Capture-DR to Shift-DR. 12 cycles in Shift-DR (the last with TMS=1 to move out of Shift-DR) starting at 2.9μs shift in the sequence 0-0-1-0-0-1-1-1-0-0-0-0 on TDI, the value specified, least significant bit first. The final TMS=1 moves the state to Exit1-DR, followed by another TMS=1 to move to Update-DR. Completion can be signaled at this point, at time 4.1μs.

In this example the bits being shifted out on TDO can also be seen. The ORPSoC debug unit always shifts out the CRC as the last 8-bits, and the sequence 0-1-1-1-0-0-0-0 can be seen as the final bits on TDO, which is the original 8-bit CRC (00001110) in least significant bit first.

Note how the bits are delayed half a cycle from the TDI bits, because TDO changes on the falling edge of TCK (and on this cycle accurate trace will be shown on the following rising edge). Thus the final bit is picked up as the Exit1-DR state is entered.