Both examples in this chapter use the OpenRISC Reference Platform System-on-Chip, ORPSoC ([6]). A cycle accurate SystemC model was generated automatically from the source using Verilator ([8]).

ORPSoC features a JTAG interface with a number of user register which drive its debug unit. These examples show the result of resetting the unit, writing a register less than 64-bits long and reading a register more than 64-bits long.

The SystemC model consists of four modules: the ORPSoC module created by Verilator (class Vorpsoc), a reset signal generator (class ResetSC), the JTAG module using the interface described in this application note (class jtagSC) and a simple driver module to inject JTAG requests (class JtagDriver). The module structure and their interconnects are shown in Figure 4.1.

Figure 4.1.  Module structure for the ORPSoC JTAG example

The clock is provided by a sc_clock and used to drive both the system clock of ORPSoC and the JTAG TCK signals. The reset generator, ResetSC generates a reset signal for a predefined number of clock cycles after time zero. The two outputs offer active high (rst) and active low (rstn) versions, synchronous with each other.