The Verilog hierarchy is shown in Figure 3.2.

Figure 3.2.  ORPSoC Verilog module hierarchy.

The main hierarchy is the ORPSoC. The device under test (DUT) starts at orpsoc_fpga_top. This instantiates the modules for the bus interconnect (tcop_top), the CPU/debug subsystem, the flash & SRAM memory subsystem and the peripheral subsystem.

For event driven simulation with Icarus Verilog, the DUT is instantiated by the top level test bench, orpsoc. Alongside this sits the monitor module, or1200_monitor, which implements the l.nop functionality. For the Verilator model, these functions will be provided by SystemC modules.

The files for this example are provided as a single compressed tar file, and include a snapshot of the current ORPSoC source tree for convenience. However the ORPSoC source may be downloaded from www.opencores.org and used independently if preferred.

The code is set up, so the ORPSoC code is not changed. Any files that are changed are placed in mirror directories in the custom code, and preferentially selected when building the model by specifying the search path.

Caution

ORPSoC is constructed from several different projects (the CPU, the debug unit, the peripherals etc). Each has source code in its own directory, and each directory has its own timescale.v file which is included. When the various components are brought together, the header search paths (i.e. +incdir+ directories) are combined. However since the timescale file has the same name in each component (timescale.v) there is no guarantee that a component will actually include its intended timescale file. This is a potential source of confusion, but the current arrangement works, so has not been changed.