3.6.1. Distribution Code Organization

The code is organized into a number of directories:

Top level directory: This contains the Makefile used to build the system and the source files for the main Verilator test bench in SystemC (OrpsocMain.cpp and OrpsocMain.h).
orp_soc: This directory is a snapshot of the current ORPSoC source tree from www.opencores.org. Described in more detail below.
local: This directory is a shadow of the orp_soc directory. Changed versions of files are placed here (thus preserving the original source), and preferentially selected when building the model by setting the search path.
sim: This directory contains the command files used to build event driven simulation models using Icarus Verilog (*.scr).
sysc-modules: This directory contains hand written SystemC modules which are part of the SystemC test bench (Or1200MonitorSC and ResetSC).
verilator-model: This directory contains the command files to build the various Verilator models (*.scr), a class, OrpsocAccess, giving access to signals inside the Verilator model, and a SystemC module, TraceSC, generating VCD trace information if required.

Original ORPSoC Source Code Organization

The original ORPSoC source tree snapshot can be found in directory orp_soc of the distribution. The subdirectories are:

bench

The test bench code. Subdirectory verilog contains ORPSoC specific Verilog code. These include timescale.v specifying the `timescale for use across the system, and bench_defines.v setting system wide `define constants.

doc

Documentation about ORPSoC. The top level file ORP.txt specifies a memory map and interrupt assignment, but this does not match the actual memory map used in the Verilog RTL (see Section 3.1).

Separate subdirectories, dbg_interface, ethernet, or1200 and uart16550 document their corresponding sub-systems and peripherals.

rtl

This is the Verilog RTL code for ORPSoC. The main verilog subdirectory contains the top level FPGA header file, xsv_fpga_defines.v, and module definition, xsv_fpga_top.v, together with two "glue logic" modules, tc_top.v and tdm_slave_if.v.

Separate subdirectories audio, dbg_interface, ethernet, mem_if, or1200, ps2, ssvga and uart16550 contain the Verilog for the core CPU, debug unit, Flash and SRAM memory interfaces and peripherals. Directories with older versions of the RTL for some peripherals are also present.

sw

This is the target software, which can be loaded into the ORPSoC Flash memory for various tests. They are all designed to be compiled using the OpenRISC 1000 tool chain (see [6]).

The utilities in the utils directory must be built first, followed by the support libraries in support. The other directories may be built in any order. In general versions of the software are provided for use with and without caches.

Caution

	Caution
There does seem to be an assumption in these code examples that ORPSoC is built with multiply (`l.mul`, `l.mulu`) and divide (`l.div`, `l.divu`) instructions. Unfortunately this is not consistent with the default settings in the Verilog RTL.

There does seem to be an assumption in these code examples that ORPSoC is built with multiply (l.mul, l.mulu) and divide (l.div, l.divu) instructions.

Unfortunately this is not consistent with the default settings in the Verilog RTL.