bench/verilog/bench_defines.v. The clock half-period is set to 50 ns, corresponding to a clock rate of 10MHz.

bench/verilog/or1200_monitor.v. The standard ORPSoC implementation includes a great deal of logging functionality. This is not of relevance to the typical applications of cycle accurate modeling in firmware development. The custom version is stripped down to provide just the custom l.nop functions (see Section 3.5).

bench/verilog/orpsoc_bench.v. The original top level module was bench/verilog/xess_top.v and represented a top level wrapper for a Xilinx FPGA, and incorporated Verilog models of some of the peripheral behavior.

The intention for the Verilator SystemC model is that any external functionality is provided by SystemC modules. orpsoc_bench.v is a rewrite of xess_top.v to provide a thin test bench to allow the model also to be run under event-driven simulation.

In this simple implementation, the external ports are tied off, but could be connected to Verilog behavioral models in the future.

rtl/verilog/orpsoc_fpga_top.v. This is the top level of the FPGA being modeled, and based closely on xsv_fpga_top.v in the ORPSoC source. However some aspects have been simplified. There is no boot CPLD, or TDM conversion. Since all memory is internal, there is no need for external memory ports for the Flash and SRAM.

This top level module of the actual device is completely independent of any Verilog test bench (since with Verilator it will use a SystemC test bench), so does not include bench_defines.v.

rtl/verilog/orpsoc_fpga_defines.v. This is a close derivative of the original rtl/verilog/xsv_fpga_defines.v. However the `define TARGET_VIRTEX is removed, since no Xilinx (the manufacturer's of the Virtex FPGA range) IP is used. A minor bug in the definition of APP_ADDR_PERIP is also corrected.

rtl/verilog/or1200_defines.v. This customizes the CPU for this application. Even though it is notionally a FPGA design, caches and MMUs are enabled (by defining OR1200_NO_DC, OR1200_NO_IC, OR1200_NO_DMMU and OR1200_NO_IMMU) and hardware division is enabled (by defining OR1200_IMPL_DIV)

rtl/verilog/ssvga/ssvga_fifo.v, rtl/verilog/ssvga/ssvga_top.v, rtl/verilog/ssvga/ssvga_dpram_4x8x16.v and rtl/verilog/ssvga/ssvga_dpram_4x16x16.v. Almost the entire ORPSoC design provides options to use different manufacturer's RAM block models, or a generic flip-flop model. This is managed through `ifdef directives, using `define values from the main header files.

The exception is the VGA peripheral, which assumes availability of Xilinx RAMB4 models. To fix this, modified versions of the two VGA source files (rtl/verilog/ssvga/ssvga_fifo.v and rtl/verilog/ssvga/ssvga_top.v), together with suitable generic dual ported RAM blocks (rtl/verilog/ssvga/ssvga_dpram_4x8x16.v and rtl/verilog/ssvga/ssvga_dpram_4x16x16.v).