Chapter 8. Summary

This application note has shown how to build and optimize a cycle accurate model of a complete SoC in SystemC using Verilator. The steps can be summarized as:

Establish a baseline model using event driven simulation, against which subsequent Verilator models can be compared.
Build a baseline Verilator model starting from the same source hierarchy. Make RTL modifications where necessary to meet Verilator's language requirements, and disable warnings at this stage.
Show that any RTL changes still work correctly under event driven simulation.
Rerun Verilator with warnings enabled. In general fix all warnings in new code, but only fix UNOPTFLAT and UNOPT in working legacy code.
Show that any RTL changes still work correctly under event driven simulation.
Optimize the C++ compilation. Start using either -O1 or -Os with the GNU C++ compiler.
If time permits use profile directed compilation of the C++ and -O3.
Profile the finished model using gprof and Verilator's post-analysis utility. Consider disabling or optimizing any modules that are a serious performance bottleneck.

The starting point in this example was an event driven simulation of the SoC running at 1.4kHz. An initial Verilator model required a small number of changes to the RTL and achieved over 40kHz.

However, after following the steps in this tutorial, the final optimized model was capable of running at nearly 130kHz. These results are shown graphically in Figure 8.1.

Figure 8.1. Summary of model performance for ORPSoC

The result is a cycle accurate SystemC model of a complete SoC, with a performance which makes low-level firmware development a quite feasible activity.

Suggestions for corrections or improvements are welcomed. Please contact the author at jeremy.bennett@embecosm.com.