This final example shows the JTAG interface's facilities for handling large data registers. This example shows a read from one of the ORPSoC JTAG 73-bit debug registers

The code to read a register also involves scanning in data, and for ORPSoC that data must have a correct CRC to be accepted. The code is as follows:

sc_core::sc_event *actionDone = new sc_core::sc_event();
uint64_t dRegArray[2];
memset (dRegArray, 0, 16);
dRegArray[0] |= data;
uint8_t crc_in = crc8 (dRegArray, 65);
insertBits (crc_in, 8, dRegArray, 65);

TapActionDRScan *dRScan = new TapActionDRScan (actionDone, dRegArray, 73);
tapActionQueue->write (dRScan);
wait (*actionDone);

dRScan->getDRegOut (dRegArray);
delete dRScan;
delete  actionDone;
      

The 73-bit data is built up in the array dRegArray from a value (bits 0-64) and a CRC (bits 65-72). The action is created as a new instance of TapActionDRScan, passing in a SystemC event for signaling completion, with the data value array and the data register length.

After completion, the result is retrieved back into dRegArray using the getDRegOut method of the TapActionDRScan class.

The results are again traced in a VCD and shown in Figure 4.5.

Figure 4.5.  VCD trace of a "large" JTAG data register read request

The data register read action commences at 23.4μs. The TAP state machine is currently at Update-IR from the previous write of an instruction register. A TMS sequence of 1-0-0 takes the state through Select-DR-Scan and Capture-DR to Shift-DR. There are then 73 cycles in Shift-DR (the last with TMS=1 to move out of Shift-DR) starting at 23.7μs. The value is shifted out least significant bit first on TDO (one cycle delayed, since it is on the negative edge). The value is 0x0620000000200000000.

The final TMS=1 moves the state to Exit1-DR, followed by another TMS=1 to move to Update-DR. Completion can be signaled at this point, at time 31.1μs.